1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to dynamic memory arrays incorporating a memory cell plate biased at a voltage near the bit line equilibration voltage.
2.Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). Frequently, the bit lines of such a dynamic memory array are equilibrated to a voltage near one-half of the power supply voltage (i.e., "V.sub.DD /2 equilibration") and the cell plate for all the memory cells is biased also at the mid-VDD voltage level.
During power-up of an integrated circuit incorporating a such a dynamic memory array, power-up circuitry frequently drives the voltage of the memory cell plate to its desired value. For example, for a circuit operating at a VDD of 2.5 volts, the memory cell plate may be driven during power-up to a typical voltage of 1.25 volts and maintained at that voltage. The true and complement bit lines of the memory array are equilibrated together, and also frequently equilibrated to the memory cell plate voltage.
During power-up, when the memory cell plate is driven from ground to its operating voltage of 1.25 volts, each of the internal memory cell nodes is capacitively coupled by the cell plate, and each internal node follows the cell plate and arrives at substantially the same voltage of 1.25 volts (for this example). At the same time, the true and complement bit lines may also be driven to 1.25 volts in preparation for the first internal memory operation. When the first internal memory operations occur, the voltage in each memory cell is substantially equal to the voltage of its associated bit line. Consequently, when the word line is driven high, there is no differential voltage developed between a true bit line and its complement bit line, and the associated bit line sense amplifier is strobed with substantially no signal. As is true with any latching circuit, a meta-stable condition may easily arise, during which the bit line sense amplifier cannot quickly determine which way to latch. When operated with fast cycle times, a memory array may not have enough time to wait for the meta-stable latches to eventually "decide" which way to latch. As a result of this indecision, the first write cycle to address a given word line may establish very poor voltage levels in memory cells of the given word line.
Initialization cycles are frequently performed after the power supply voltages are stable to ensure that peripheral circuits are "exercised" a few times to properly and accurately set the voltages of various nodes. Such cycles are, however, externally-controlled cycles which may presume correct operation of the bit lines and sense amplifiers. In circuits with delicate timing or other constraints, the possibility of such meta-stable operation, even during initialization cycles, may be extremely undesirable.